library verilog;
use verilog.vl_types.all;
entity cmsdk_ahb_cs_rom_table is
    generic(
        BASE            : vl_logic_vector(31 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
        JEPID           : vl_logic_vector(6 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
        JEPCONTINUATION : vl_logic_vector(3 downto 0) := (Hi0, Hi0, Hi0, Hi0);
        PARTNUMBER      : vl_logic_vector(11 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
        REVISION        : vl_logic_vector(3 downto 0) := (Hi0, Hi0, Hi0, Hi0);
        ENTRY0BASEADDR  : vl_logic_vector(31 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
        ENTRY0PRESENT   : vl_logic := Hi0;
        ENTRY1BASEADDR  : vl_logic_vector(31 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
        ENTRY1PRESENT   : vl_logic := Hi0;
        ENTRY2BASEADDR  : vl_logic_vector(31 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
        ENTRY2PRESENT   : vl_logic := Hi0;
        ENTRY3BASEADDR  : vl_logic_vector(31 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
        ENTRY3PRESENT   : vl_logic := Hi0
    );
    port(
        HCLK            : in     vl_logic;
        HSEL            : in     vl_logic;
        HADDR           : in     vl_logic_vector(31 downto 0);
        HBURST          : in     vl_logic_vector(2 downto 0);
        HMASTLOCK       : in     vl_logic;
        HPROT           : in     vl_logic_vector(3 downto 0);
        HSIZE           : in     vl_logic_vector(2 downto 0);
        HTRANS          : in     vl_logic_vector(1 downto 0);
        HWDATA          : in     vl_logic_vector(31 downto 0);
        HWRITE          : in     vl_logic;
        HREADY          : in     vl_logic;
        ECOREVNUM       : in     vl_logic_vector(3 downto 0);
        HRDATA          : out    vl_logic_vector(31 downto 0);
        HRESP           : out    vl_logic;
        HREADYOUT       : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of BASE : constant is 2;
    attribute mti_svvh_generic_type of JEPID : constant is 2;
    attribute mti_svvh_generic_type of JEPCONTINUATION : constant is 2;
    attribute mti_svvh_generic_type of PARTNUMBER : constant is 2;
    attribute mti_svvh_generic_type of REVISION : constant is 2;
    attribute mti_svvh_generic_type of ENTRY0BASEADDR : constant is 2;
    attribute mti_svvh_generic_type of ENTRY0PRESENT : constant is 1;
    attribute mti_svvh_generic_type of ENTRY1BASEADDR : constant is 2;
    attribute mti_svvh_generic_type of ENTRY1PRESENT : constant is 1;
    attribute mti_svvh_generic_type of ENTRY2BASEADDR : constant is 2;
    attribute mti_svvh_generic_type of ENTRY2PRESENT : constant is 1;
    attribute mti_svvh_generic_type of ENTRY3BASEADDR : constant is 2;
    attribute mti_svvh_generic_type of ENTRY3PRESENT : constant is 1;
end cmsdk_ahb_cs_rom_table;
